1. Field of the Invention
The present invention relates to a multilayer interconnection structure semiconductor device adopting damascene technology, which prevents degradation of reliability of the interconnection due to stress migration (SM).
2. Description of the Related Art
When a semiconductor device having a damascene interconnection is continuously in operation for a long time, a stress migration is generated due to generated heat, which generates voids in a via contact or in a lower-layer interconnection portion under the via contact. The generation of voids decreases the reliability of the damascene interconnection reliability. Conventionally, a multi via plug in which plural via plugs are formed in the same connection portion of the interconnection is used in order to prevent the deterioration of damascene interconnection reliability due to the stress migration (see Jpn. Pat. Appln. KOKAI Publication No. 11-74271). There is also proposed a structure having plural dummy via plugs (see Jpn. Pat. Appln. KOKAI Publication No. 2000-119969). However, in such conventional methods, there is a possibility that voids are generated in the via plug to be connected or in the lower-layer interconnection portion under the via contact to be connected, and the deterioration of the damascene interconnection reliability is not sufficiently prevented.